The CSYN verilog compiler and other tools

Abstract

The CSYN Verilog compiler was written by Dr Greaves in early 1994 as a vehicle for research in logic synthesis algorithms and to support experimental extensions to the Verilog language to test high-level specification techniques. A basic version of CSYN is in use at a number of local companies for industrial PPGA design. This paper describes CSYN and its use with Xilinx devices for teaching. To extend this work, we are defining formal semantics for Verilog, both for simulation and compilation into hardware. This paper reports the performance of CSIM, an X-windows Verilog simulator based on the formal simulation semantics and expresses the desire for a general purpose semantics for Verilog, which can help prove the equivalance of different implementations of a module.