GPGPU implementation of parallel memetic algorithm for VLSI floorplanning problem

Abstract

The VLSI Physical design floorplanning is the process where circuit description is converted into geometric description. This NP-Optimization problem with non-slicing blocks is very hard to solve. Memetic algorithms are used to solve NP-Optimization problems. Memetic algorithms are a family of meta-heuristic search algorithms in which a rule-based representation of Local Search (LS) is co-adapted alongside the candidate solutions within a hybrid evolutionary system. However, they may execute for a long time for difficult problems, because of several fitness evaluations. A promising approach to overcome this limitation is to parallelize these algorithms. In this paper, we propose to implement a parallel Memetic Algorithm (MA) on Graphical Processing Units. The General Purpose Graphical Processing Unit (GPGPU) is the complete parallel hardware which is best used for the Parallel Computing. The Parallel Memetic Algorithm we followed for an application perspective is a modified or hybrid genetic algorithm with extensive attributes to local search. The Parallel Memetic Algorithm operator gives a perfect exploration in the available search area and it is typical for addressing a modular assignment problem. It reduces the time efficiently for execution which is a boon for VLSI industry where we don't have to spend more weeks for Physical design to be completed. We perform experiments to compare our parallel MA with an ordinary MA and demonstrate that the former is much more effective than the latter. Both fitness evaluation and genetic operations are spread over the GPU cores, allowing for the efficient processing of very large datasets. The parallel nature of Memetic algorithm can be best harnessed with help of GPGPU and significant changes in execution time and optimization are shown for VLSI Floorplanning problem. © 2011 Springer-Verlag Berlin Heidelberg.