A spike decoding scheme for Address Event Representation (AER)-based transmission in Spiking Neural Network (SNN) emulators is introduced. The proposed scheme is a modified associative memory based on an efficient use of BRAM, supporting connectivity upgrade in real-time for hardware implementations of evolutionary networks. After analysing the different options and selecting the most efficient one, a prototype example based on FPGA is provided together with a novel hashing technique to demonstrate a compact on-chip solution for implementing inter-chip connectivity in SNN.
CITATION STYLE
Zapata, M., & Madrenas, J. (2016). Compact associative memory for AER spike decoding in FPGA-based evolvable SNN emulation. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 9886 LNCS, pp. 399–407). Springer Verlag. https://doi.org/10.1007/978-3-319-44778-0_47
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