Skip to main content
Conference Proceedings

Using formal verification techniques to reduce simulation and test effort

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (2001) 2021 LNCS 465-477
DOI: 10.1007/3-540-45251-6_27
3Citations
Citations of this article
4Readers
Mendeley users who have this article in their library.
Get full text

Abstract

This paper describes an experiment in using formal methods in an industrial context. The goal is to use formal verification techniques in order to alleviate the simulation and test activities. The application is a flight control computer of the Airbus A340. © Springer-Verlag Berlin Heidelberg 2001.

Cite

CITATION STYLE

APA

Laurent, O., Michel, P., & Wiels, V. (2001). Using formal verification techniques to reduce simulation and test effort. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2021 LNCS, pp. 465–477). Springer Verlag. https://doi.org/10.1007/3-540-45251-6_27

Register to see more suggestions

Mendeley helps you to discover research relevant for your work.

Already have an account?

Save time finding and organizing research with Mendeley

Sign up for free