If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results. © Springer-Verlag Berlin Heidelberg 2005.
CITATION STYLE
Zuber, P., Gritzmann, P., Ritter, M., & Stechele, W. (2005). The optimal wire order for low power CMOS. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3728 LNCS, pp. 674–683). Springer Verlag. https://doi.org/10.1007/11556930_69
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