Low error, efficient fixed width squarer using hybrid LUT-based architecture

Abstract

This paper presents the design of low error and efficient fixed width squarer employing hybrid LUT-based architecture which can be used for future DSP applications. By applying the mathematical identities and hybrid architecture, the mean error and mean squarer error of proposed squarer are reduced by up to 40% compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of squaring circuits. The implementations results for both FPGA hardware and 0.18-μm CMOS technology are also reported and discussed. © 2011 Springer-Verlag.