Exploiting parallelization on address translation: Shared page walk cache

Abstract

Current processors carry out a Page Table Walk to translate a virtual address into a physical address. This process requires several memory accesses to retrieve the entry from each of the levels of the Page Table Tree. As each main memory access has a large latency, the address translation process may penalize significantly the system performance. Translation Lookaside Buffers (TLBs) avoid completely these accesses by storing the most recent translations. But on a TLB miss a Page Table Walk is required. An effective way to accelerate it is introducing a cache inside/near the MMU to store partial translations. Recent works have shown the advantages of using a Page Walk Cache on the service of a single core. In this paper we propose a Page Walk Cache shared among the cores of a CMP and analyze its behavior and how it improves performance for parallel applications, comparing it to a private Page Walk Cache scheme. Evaluation results show that shared PTWC increases up to a 19.8% the hit-rate, leading to a TLB miss latency reduction of up to 12.2%, when compared to a private PTWC. © 2014 Springer-Verlag Berlin Heidelberg.