Novel shannon-based low-power full-adder architecture for neural network applications

Abstract

This paper proposes novel low-power full-adder cell to be used as Shannon adder in the neural network applications. By using the Shannon's theorem, the gate count is reduced, thereby the total chip area gets minimized. Hence, the power also gets reduced to a considerable amount. The designs are implemented using synthesis tool which results in significant reduction in area and power for the modified Shannon-based full-adder cell when compared with multiplexing control input technique (MCIT)-based full-adder cell. © 2014 Springer India.