Impact of code density on instruction cache performance.

Abstract

The widespread use of reduced-instruction-set computers has generated a lot of interest in the tradeoff between the density of an instruction set and the size of the instruction cache. The author presents and justifies a method that predicts the cache performance for a wide range of architectures, based on the miss rate for a single architecture. He applies the method to a number of cache organizations and finds that changes in code density can have a great impact on memory traffic, but that modest improvements in code density do not reduce program execution time significantly in a well-balanced system.