A compact charge-based propagation delay model for submicronic CMOS buffers

Abstract

We provide an accurate analytical expression for the propagation delay and the output transition time of submicron CMOS buffers that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in deep-submicron technologies. The model is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.35μm and a 0.18μm process technologies show significant improvements over previously-published models.