High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system

Abstract

We describe the first iteration of a comprehensive model with which we can investigate the practical limits on optical bus bandwidth and number of bus processing modules for given signal power. The selection algorithm will ultimately allow programmable evaluation of system parameters bus bandwidth, optical power budget, electrical power budget, number of modules and space consumption for an optimal design that is suitable for on-the-fly system reconfiguration.