Design and Implementation of Hybrid DC-DC Converter: A Review

Abstract

The advancement in Power Management Integrated Circuit (PMIC) has driven the dc-dc conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low-power density, and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.