Gate matrix layout revisited: Algorithmic performance and probabilistic analysis

Abstract

We consider the gate matrix layout problem for VLSI design, and improve the time and space complexities of an existing dynamic programming algorithm for its exact solution. Experimental study indicates the requirement of enormous computation time for exact solutions of even small size matrices. We derive an expression for the expected number of tracks required to layout in gate matrix style based on a probabilistic model. A local search approximation algorithm is studied experimentally and found to perform reasonably well on average.