Multi-arc processor—harnessing pseudo-concurrent multiple instruction set architecture (Isa) over a single hardware platform

Abstract

Developers, in order to quench the needs of powerful yet efficient processors, are developing processors with multiple cores where each core may or may not serve the same purpose. To achieve that different instruction set architectures (ISAs) are incorporated in some specific cores. Such an example is the modern-day artificial intelligence-central processing unit (AI-CPU), which not only have multiple cores but also dedicated neural processing units (NPUs) and graphics processing units (GPUs). These special purpose processing units (PU) are designed with different ISAs to handle a complex job like matrix multiplication as a dedicated instruction. Such augmentation comes at a cost of extra hardware, multiple types of interfacings and resource requirements. To reduce this, research is being done to try to develop customizable ISAs which can be customized in various dimensions and can be thrown into different cores. The aim of this work is to introduce Multi-Arc, a new approach to design processors with heterogeneous ISAs by enabling the same hardware design to support multiple and totally different ISAs which can be switched both implicitly and explicitly as per need.