On the reduction of partial products using wallace tree multiplier

Abstract

In order to carry out any arithmetic operation, a basic multiplication operation plays a vital role. Multiplication of any signed (or) unsigned integers can be done using a multiplier. Speed is a major corner in any processing system which in turn depends on the multiplier which acts as a basic building block. There are wide varieties of multiplier architectures that are possible multiplier among them but it cannot perform operations faster. Another possible multiplier is the “Wallace” tree multiplier which can perform operations faster, but it can give fruitful results for unsigned integers. Wallace tree multiplier gives not only speed but also a reduce delay with the help of carry save algorithm and also it uses full adders. Verilog code is simulated and designs are synthesized using Xilinx tool. In this paper, Wallace tree multiplier is compared with conventional multiplier to prove the speed of the Wallace tree multiplier as well the reduced power consumption.