Architecture at the End of Moore

Abstract

Computer architecture in recent years shifted focus from performance to power efficiency (a combined metric or performance and energy consumption). For decades architects translated Moore’s law into performance, but we are now close to hitting two major “walls”: The first is the “power wall,” or our inability to significantly reduce power consumption (and more importantly power density). The power wall is likely to lead us to a “dark silicon” future where the majority of the transistors on a chip will have to be turned off because of power constraints. The second is the “memory wall.” Because, fundamentally, our current memory technology can be fast or vast, but not both at the same time, we have to rely on a complex memory hierarchy which, nevertheless, has significant limitations. In addition to power and performance, architects also worry about reliability. As we scale to very small feature sizes, devices become increasingly unreliable. A new trend that is emerging, however, is to embrace unreliability rather than fight it. This chapter discusses the challenges computer architects are facing today and the possible connections at the architectural level with novel devices that are in development.