Enabling Processes and Integration

Abstract

Integrating a process on a chip requires a thorough and, throughout the development cycle, continuous understanding of how it will be applied. This includes the definition of a set of required components, component parameters and their tolerances, range of operating temperature, reliability expectations, set of available tools and their limitations at the time of production, and overall cost. The integration cycle begins with the definition of a full process flow. Process and device simulators are utilized to optimize the flow and ensure that it will satisfy nominal values for all parameters of the required components. Experimental short-loops are then run to evaluate individual process modules. These loops can require special test structures that may be part of a full test-die. Simulations and experiments are run in parallel to ensure the feasibility of a full process flow. A complete test die is then designed to be utilized for a full process-flow. The test-die typically contains structures that address component parameters and their tolerances, reliability structures, yield structures, process monitors, failure analysis structures, modeling structures, and sub-circuits The chapter begins with a description of a typical {CMOS} logic process flow, applicable to {MOSFETs} of ˜0.18μm channel length. This will be referred to as the “conventional process.” A conventional {BiCMOS} process follows, that is applicable to analog/mixed-signal designs. The flow utilizes several unit-process concepts that are described in [1] and the references therein. Only a brief review of selected “conventional” unit processes is presented in this chapter. The second part of the chapter focuses on advanced enabling processes, applicable to structures of nanoscale dimensions