A FPGA-based hardware architecture approach for real-time Fuzzy edge detection

Abstract

Edge detection is used on most pattern recognition algorithms for image processing, however, its main drawbacks are the detection of unreal edges and its computational cost; fuzzy edge detection is used to reduce false edges but at even higher computational cost. This paper presents a Field Programmable Gate Array (FPGA)-based hardware architecture that performs a real-time edge detection using fuzzy logic algorithms achieving a decrease in the amount of unreal edges detected while compensating the computational cost by using parallel and pipelining hardware design strategies. For image processing testing, image resolution is set to 480 × 640 pixels at 24 fps (frames per second), thus real-time processing requires 7,372,800 fuzzy logic inference per second (FLIPS). The proposed fuzzy logic edge detector is based on the morphological gradient; this algorithm performs the edge detection based in the gradient operator, getting vectors of edge direction, were the magnitude of these vectors determines if the pixel is edge or not. The hardware architecture processes each frame pixel by pixel with grayscale partial image inputs, at 8 bits resolution, represented with a 3 × 3 pixels matrix; subsequently the architecture executes the stages of the fuzzy logic system: fuzzification, inference, and defuzzification, however, taking advantage of the FPGAs versatility, the dedicated hardware-based processing is executed in parallel within a pipeline structure to achieve edge detection in real time. The real-time fuzzy edge detector is compared with several classic edge detectors to evaluate the performance in terms of quality of the edges and the processing rate in FLIPS.