IMPLEMENTATION OF PRECISE INTERRUPTS IN PIPELINED PROCESSORS

Abstract

An imerrupt is precise if the saved process state corresponds with the sequcnnal model of program execution where one instruction completes before the next begins. In a pipelined processor, precise interrupt are diffcult to achive because an instruction may be inirirmd before us predecessors have been completed. This pager describes and evaluates solunons IO the precise interrupt problem in pipclincd proccs- SOCS. The prccrse tntcrrupt problem is first described. Then live solutions are discussed tn detail. The first forces mstructions to complcte and modil) the process SUIC in archiIaIural order. The other four allow instructions IO complete in any order. bu1 additional hardware is used so IhaI a precise SUIC can bc restored when an interrupt occurs. All the methods are drscussed in the context of a parallel pipeline structure. Simulauon resuhs based on the CRAY-IS solar archueaurc are usal IO show IhaI. a1 Hess. the first solulion results in a performance degradation of about 16%. The rcmnining four solulions offer similar performance, and Ihrcc of them rcsul1 in as linle as a 3% performance loss. Several cxtenstons. including virtual memory and linear pipeline structures, arc briefly discussed.