Tailoring potentials by simulation-aided design of gate layouts for spin-qubit applications

Abstract

Gate layouts of spin-qubit devices are commonly adapted from previous successful devices. As qubit numbers and device complexity increase, modeling new device layouts and optimizing for yield and performance become necessary. The simulation tools used in the advanced semiconductor industry need to be adapted for smaller structure sizes and electron numbers. Here, we present a general approach to electrostatically modeling new spin-qubit-device layouts, considering gate voltages, heterostructures, doping, reservoirs, and an applied source-drain bias. We identify key challenges in spin-qubit-device design: validating the impact on quantum-dot parameters, considering cross-coupling among gates and reservoirs, and ensuring robustness of the design to fabrication limits. We select a demanding target potential to investigate and optimize examples of gate layouts under these challenges. We verify our model by fabricating two simulated designs and indirectly probing the potential landscape through transport measurements.