Analysis of cybersecurity weakness in automotive in-vehicle networking and hardware accelerators for real-time cryptography

Abstract

The work analyses the cybersecurity weakness in state-of-art automotive in-vehicle networks and discusses possible countermeasures at architecture level. Due to stringent real-time constraints (throughput and latency) of fail-safe automotive applications, hardware accelerators are needed. A hardware accelerator design for AES (Advanced Encryption Standard)-128/256 calculation, the latter being already considered post-quantum resistant, is also presented together with implementation results in FPGA and 45 nm CMOS technology.