Stress and Strain Measurement in Stressed Silicon Lines

Abstract

Stressed Si lines are attractive conduction channels for transistors due to the improvement of the carrier velocity. The stress and strain in I pill width Si lines on top of silicon oxide have been characterized by analysing plan view Moire patterns obtained by transmission electron microscopy (TEM) and comparing them with Raman spectroscopy and X-ray diffraction results. A good agreement is found between experimental measurements and results from simulations, which validates our approach of measuring structural deformation by Moire fringes. Regions having a Si substrate thicker than 400nm produce Moire period profiles similar to the ones that would be obtained on the initial thick wafer. The relaxation of the stress at the edge of the lilies is clearly shown in Moire fringe images.