New Floating Gate Memory with Excellent Retention Characteristics

Abstract

In current flash memory, there is an inevitable tradeoff between the operation voltage and the retention time due to the incorporation of very thin tunneling layer in the device structure. In this work, a new type of robust floating gate nonvolatile memory based on 2D materials is introduced to reduce the operation voltage and promote the data retention time. By taking the advantage of a dual-gate structure, as-fabricated devices exhibit excellent performance with low operation voltage (as low as 5 V even the tunneling layer t BN  ≥ 10 nm), long retention time (on/off ratio with negligible degeneration over 10 5 s), and ultralow off-leakage current (10 −13 A, which is very attractive for ultralow-power applications). Charges trapped in the top gate originated from the capacitive coupling between the back and top gates are found to be responsible for the nonvolatile behavior. The new charge trapping mechanism, which is distinguished from that in the conventional single-gate memory devices, enables charge tunneling through a thicker tunneling layer at a low operation voltage. The achieved MoS 2 nonvolatile memory with outstanding performances has great potentials for future information storage.