Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconfiguration. In this paper we compare several new configuration caching algorithms that reduce the latency of reconfiguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the configurations is reduced, lowering the configurable overhead.
CITATION STYLE
Sudhir, S., Nath, S., & Goldstein, S. C. (2001). Configuration caching and swapping. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 2147, pp. 192–202). Springer Verlag. https://doi.org/10.1007/3-540-44687-7_20
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