Cracking the DES Cipher with Cost-Optimized FPGA Devices

Abstract

This paper examines efficiency of hardware realizations of DES cracking engines implemented in contemporary low-cost Spartan-7 devices from Xilinx, Inc. The engines are designed for the known plaintext attack scheme and find the secret cipher key through brute-force exhaustive search of the entire key space. In order to comprehensively evaluate potential of the selected FPGA family in this task three architectures of DES decoders were tested: the standard iterative organization, the fully unrolled i.e. purely combinational one and the fully unrolled pipelined version. Various sizes of individual decipher units based on these three architectures led to evaluation of optimal ratios of unit speeds vs. their number which fit in one chip. The results are compared with other known hardware platforms and illustrate progress in the cipher cracking systems which was made possible by improvements in the new FPGA technologies.