The Common-Gate Configuration

Abstract

In the common gate configuration, the gate-to-source and the drain-to-source voltages, VGS and VDS, vary with the source-to-substrate voltage VS. As a result, the compact model parameters require continuing updating. Figure 7.1 displays the drain current versus the source voltage VS of the 100 nm N-channel transistor considered in the previous chapter taking advantage of updated n, VTo and ISuo parameters. The gate- and drain-to-substrate voltages are constant and respectively equal to 0.9 and 1.0 V. The currents predicted by the compact model with and without mobility degradation are represented respectively by the continuous and dashed curves. Crosses represent the ‘semi-empirical’ drain current. When VS is small, the impact of mobility degradation is considerable for the gate-to-source and drain-to-source voltages are large. As VS increases, the two curves concur progressively until they merge in weak inversion giving birth to the distinctive weak inversion straight line.