Design of the configurable watch dog timer using FPGA in space probe application

Abstract

Watchdog timer is a simple timer circuit. It is an indispensable part and is of paramount importance when coming to the embedded system. Most implementations of watch dog are simply based on simple feed dog strategy covering merely limited abnormal states of program. There are different types of watch dog timers due to the increasing need. They include Standard watchdog timer, Windowed watch dog timer, sequenced watch dog timer. But an effective watch dog timer should be able to detect all abnormal software modes and bring the system back to a known state. In addition to that, it must have its own clock and should be capable of providing a hardware reset on timeout to all the peripherals which the current timers lag. Hence the windowed watchdog timer where the window periods can be configured during the software initialization. In the watchdog timers which are available right now is processor dependent due to which there is a increase in the timing but there is a need of a watchdog timer which has capability to cut down or reduce timing hence watchdog timer which has got service, frame and controller windows have been used, which is independent of the processor and hence the timing is reduced effectively.