Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays

Abstract

Dynamically reconfigurable Field Programmable Gate Arrays (FPGAs) offer virtually unlimited numbers of gates to an application. This technology makes feasible large applications which can be temporally partitioned, with each phase being rapidly loaded onto the chip as required. We demonstrate in this paper an automatic technique to temporally partition a parallel program. Our technique partitions along a data parallel C program’s function scopes. A configuration bit stream is generated for each function, and the host control program is generated which automatically loads the function’s configuration file as the function is entered during execution. Preliminary results show that this partitioning makes it possible to - run larger problem sets, - run programs which would not otherwise fit on the chip, and - include program-specific debug code without performance penalty. Our compiler targets the NAPA accelerator board, a PCI bus based parallel system whose processors consist of Multi Chip Modules composed of National Semiconductor CLAy™ FPGAs.