An FPGA configuration scheme for bitstream protection

Abstract

FPGAs are widely used recently, and security on configuration bitstreams is of concern to both users and suppliers of configuration bitstreams (e.g., intellectual property vendors). In order to protect configuration bitstreams against the threats such as FPGA viruses, piracy and reverse engineering, configuration bitstreams need to be encrypted and authenticated before loaded into FPGAs. In this paper, we propose a new FPGA configuration scheme that can authenticate and/or decrypt a bitstream. The proposed scheme has flexibility in choosing authentication and/or decryption algorithms and causes only a small area overhead since it utilizes programmable logic blocks to implement authentication and/or decryption circuits. © 2008 Springer-Verlag Berlin Heidelberg.