Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU

Abstract

Verification of a Floating point Unit is a challenging and unique task. Major challenges are the selection of reference model for verification and coverage domains and space of test vectors. The proposed paper considers a RISC-V compliant floating point unit modelled using a high level language, Bluespec System Verilog as Design Under Test (DUT) for verification. A reference model of floating point unit is developed in ‘C’ compliance with RISC-V ISA. To fulfil the requirements of test vector coverage domain and space, we have adopted four different kinds of test vectors schemes for verification. At first, a pseudo random verification approach is used to reduce the initial errors in design. In step-2, a RISC-V test suite was used to verify the proposed design for compliance with RISC-V ISA. In step-3, FPgen/IBM floating point test vectors were used to test for corner case test vectors, for better coverage space. Further, we adopted a unique approach to validate the RISC-V FPU in FPGA by providing the above three kinds of test vectors as inputs through ‘C’ application code on host machine. The outputs are compared with the above ‘C’ based reference model/FPgen output vectors/RISC-V test suite output vectors. In step-4, FPU on FPGA is validated using Whetstone code on host-machine FPU and redirected Whetstone floating point computations to FPU DUT on Xilinx Virtex-6 vc6lx550T FPGA device. Finally, the RISC-V FPU is integrated with dual issue out-of-order execute, in-order commit RISC-V processor and demonstrated a whetstone benchmarking application on FPGA. Major benefits of the proposed floating point verification can be extended to an application based RISC-V compliant floating point unit validation on FPGA without the use of RISC-V processor pipeline.