Enhanced portable LUT multiplier with gated power optimization for biomedical therapeutic devices

Abstract

Digital design of a digital signal processor involves accurate and high-speed mathematical computation units. DSP units are one of the most power consuming and memory occupying devices. Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices. This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit. A lookup table-based multiplier has the advantage of almost constant area requirement's irrespective to the increase in bit size of multiplier. Clock gating is usually used to reduce the unnecessary switching activities in idle circlet components. A clock tree structure is employed to enhance the SRAM based lookup table memory architecture. The LUT memory access operation is sequential in nature and instead of address decoder a ring counter is used to scan the memory contents and gated driver tree structure is implemented to control the clock and data switching activities. The proposed algorithm yields 20% of power reduction than existing.