Estimation of MOS capacitance across different technology nodes

Abstract

This paper presents an in-depth analysis of NMOS capacitances across various technology nodes and device parameters which are extracted for different operating regions namely accumulation, cutoff, saturation and triode, while keeping the aspect ratio same for each transistor. Since MOS capacitances are the key parameters for estimating process development, material selection and device modeling, this paper enlists their variation with gate-to-source voltage (VGS) while keeping drain-to-source voltage (VDS) constant. This paper also aims to present the impact of capacitance variation on device performance that includes operating speed, power consumption, delay product and so on. The simulations results have been extensively verified using HSPICE simulator @ various technology nodes.