Clustered microarchitecture simultaneous multithreading

Abstract

The excessive amount of heat that billions of transistors will produce will be the most important challenge to the design of the future chips. In order to reduce the power consumption of microprocessors, many low power architectures have been developed. However, this has come at the expense of performance, and only few low power architectures for superscalar, such as clustered architectures, target high performance computing applications. In this paper, we propose a new clustered SMT architecture which is appropriate for both multiple threads and single thread environments. We analyzed the proposed design is analyzed and compared it to conventional SMT architectures. We show that our approach significantly, reduces power consumption without significantly degrading performance. © Springer-Verlag 2003.