Architecture Optimization

Abstract

This chapter presents a framework for the high-level optimization of time-interleaved ADCs. The results show that for interleaved flash ADCs, there is an optimal value for the interleaving factor, which is a function of the load capacitance of the dynamic comparators, the ADC resolution, the sampling rate, and the static power dissipation of the resistor ladder. An extension to transistor-level circuits is discussed, and the plotted results have a similar form to those of the high-level framework.