High speed LDPC encoder architecture for digital video broadcasting systems

Abstract

In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock. © 2012 Springer-Verlag.