Porting of eChronos RTOS on RISC-V Architecture

Abstract

eChronos is a formally verified real-time operating system (RTOS) designed for embedded microcontrollers. eChronos was targeted for tightly constrained devices without memory management units. Currently, eChronos is available on proprietary designs like ARM, PowerPC, and Intel architectures. eChronos is adopted in safety critical systems like aircraft control system and medical implant devices. eChronos is one of the very few system softwares not been ported to RISC-V. RISC-V is an open-source instruction set architecture (ISA) that enables a new era of processor development. Many standard operating systems, software toolchain has migrated to the RISC-V architecture. According to the latest trends [1], RISC-V is replacing many proprietary chips. As a secure RTOS, it is attractive to port on an open-source ISA. SHAKTI and PicoRV32 are some of the proven open-source RISC-V designs available. Now having a secure RTOS on an open-source hardware design, designed based on an open-source ISA makes it more interesting. In addition to this, the current architectures supported by eChronos are all proprietary designs [2], and porting eChronos to the RISC-V architecture increases the secure system development as a whole. This paper presents an idea of porting eChronos on a chip which is open-source and effective, thus reducing the cost of embedded systems. Designing a open-source system that is completely open-source reduces the overall cost, increased the security, and can be critically reviewed. This paper explores the design and architecture aspect involved in porting eChronos to RISC-V. The authors have successfully ported eChronos to RISC-V architecture and verified it on spike [3]. The port of RISC-V to eChronos is made available open-source by authors [4]. Along with that, the safe removal of architectural dependencies and subsequent changes in eChronos is also analyzed.