Logical circuits design education based on virtual verification panel

Abstract

The paper presents a novel method for teaching courses about logical circuits. Attracting students' interest is an issue that is being addressed in all courses. In general, students are more interested in doing practical exercises then learning theory and calculating or designing things on a piece of paper. In courses devoted to logic circuits design it is especially important that the students have the possibility to verify their designs and to experiment with various variations. Using universal virtual verification panel, the lessons can be more understandable. Our solution has limitation for logical gates as formerly had physical verification panels but also many other features which can be used during education. Experimental results show, that 90.2 % of students think that our solution is better than the old one [1]. © 2013 Springer Science+Business Media.