Optimization of ASIC design cycle time

Abstract

Due to the high complexity of modern circuit designs, verification has become the major bottleneck of entire design process. Common industry estimates are that functional verification constitutes near 70% of the total effort on any ASIC project. In this paper, we have tried to describe various ways to optimize verification time, comparing their effect on verification time and complete design cycle, with the conclusion of selecting modeling as better mechanism. The present paper has proved modeling as the best approach for optimizing ASIC design cycle with the experimentation taking a case-study. © 2010 Springer-Verlag Berlin Heidelberg.