Register Transfer Level Disparity generator with Stereo Vision

Abstract

This tool can generate binary files for Xilinx FPGAs for “Stereo Vision-based disparity generation”. With related vendor tools this project can be ported to other types of FPGAs (such as Intel technology). Implementation is done using VHDL and Verilog hardware description languages. The tool is available in 3 stages 1). Functional Verification 2). Stereo Camera integration 3). Disparity Generation. Documentation is available for users who are interested in modifying for different platforms. Components that are used during physical setup are explained in the documentation and based on the requirements they can be changed. In order to use this tool, the user must have prior experience in hardware description languages, experience in Xilinx tools will be an additional advantage.