Power-Aware test data compression and BIST

Abstract

The test data volume for manufacturing test of modern devices is increasing rapidly. This is due to the facts that the transistor count for these chips is increasing exponentially and the use of advanced technology introduces new physical and timing-related defects, which require new types of test. It is well known that power consumption during test is much higher than in the functional mode due to increased switching activity in test mode. Therefore, efficient techniques that minimize both test data volume and test power consumption are required. Techniques such as test data compression and built-in-self-test (BIST) are used commonly to handle the problem of increased test data volume. In this chapter, several low-power state-of-the-art test data compression and BIST techniques are discussed. Their advantages and disadvantages are discussed from area, performance, and power point of view. © 2010 Springer-Verlag US.