Implementation of 18-bit high-speed binary multipliers

Abstract

Multiplication is an extensively used arithmetic operation that has immense usage in signal processing and scientific applications. Multiplication is hardware intensive, and the main criteria of interests are less VLSI area, higher speed, and lower cost. Multiplication involves basically two operations, first is generating the partial products and then their accumulation, where the partial product is shifted by one bit to the right and adding with the previous partial product. The speed of multiplication can be enhanced by reducing the number of partial products or by enhancing the speed of the accumulation. Hence, in this paper, the novel study of the different fast multipliers like radix-2 or Booth algorithm, radix-4 or modified Booth algorithm is done, and implementation of 18-bit multiplier is done in Verilog (Modelsim) and compared the results in MATLAB. The SNR analysis of the multiplier of finite precision product, truncation, and rounding is done. Algorithms for reducing the hardware complexity in partial product sign extension are implemented for both radix-2 Booth multiplication and radix-4 modified Booth multiplication. The Wallace tree adder is implemented for increasing the speed of the accumulation of the partial products.