Most successful attacks against hardware implementations of cryptographic systems make use of side-channel information leakage. Recently, some attacks have been proposed against various cryptosystems, which exploit deliberate error injection during the computation process. Several error detection schemes have been proposed in order to counteract these attacks. In this paper, we add a residue-based error detection scheme to an RSA architecture and evaluate the area and latency overheads with respect to the basic architecture. © Springer-Verlag Berlin Heidelberg 2006.
CITATION STYLE
Breveglieri, L., Koren, I., Maistri, P., & Ravasio, M. (2006). Incorporating error detection in an RSA architecture. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4236 LNCS, pp. 71–79). Springer Verlag. https://doi.org/10.1007/11889700_7
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