Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

Abstract

Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover MNU cases, they incur significant hardware redundancy and more sensitive nodes due to only depending on multiple circuit instances (e.g., C-elements (CEs)). In order to obtain a balance between high tolerance capability and low overheads, in this paper, we propose a novel radiation hardened latch (RHL) based on the polarity of the radiation-induced voltage pulse (positive or negative pulse). The proposed latch is capable of tolerating any possible single node upset (SNU) and MNU cases in all considered nodes while manifesting fewer transistors and sensitive nodes. The timing (transparent and hold) function and reliability are successfully verified by simulation in TSMC 65nm bulk CMOS process. In addition, the results of the cost comparison have illustrated that the proposed RHL latch has a moderate area and power dissipation, but provides significant benefit in terms of both delay and power-delay-area-product (PDAP) among the alternative latches.