Sub-ADC Architectures for Time-interleaved ADCs

Abstract

Chapter 3 discusses the architecture of the sub-ADCs, which are used in the time-interleaved ADC. A Successive Approximation ADC (SA-ADC) can have a very good power efficiency, its sample-rate is however limited. In a conventional SA-ADC, the sample-rate is mainly limited by settling of the DAC. Overrange techniques can reduce the required DAC settling time. A new overrange technique is presented called the single-sided overrange technique. Compared to a conventional SA-ADC, it saves 58% of the settling time, and therefore it can be more energy efficient. By using multiple comparators with different accuracies in an SA-ADC with overrange, power can be saved. Look-ahead logic removes the delay of the logic out of the SA-ADC loop and increases the maximum sample-rate. An efficiency comparison between an SA-ADC and a pipeline ADC is made, based on the power consumption of comparators and opamps. For the same specifications, an SA-ADC can use roughly 10 times less power. This conclusion is supported by literature.