Systolic and scalable architectures for digit-serial multiplication in fields GF(pm)

Abstract

This contribution defines systolic digit-serial architectures for fields G(pm). These architectures are scalable in the sense that their instantiations support multiplication in different fields GF(pm) for which p is fixed and m is variable. These features make the multiplier architectures suitable for ASIC as well as FPGA implementations. In addition, the same architectures are easily applicable to tower fields GF(qm) for a given ground field GF(q), where q itself is a prime power. We simulated the basic cell of a systolic LSDE multiplier on 0.18 μm CMOS technology to verify the functionality of the architectures. Finally, we provide specific values for GF(2m) and GF(3m) fields which are of particular interest in recent cryptographic applications, for example, the implementation of short signature schemes based on the Tate pairing. © Springer-Verlag Berlin Heidelberg 2003.