NSP: A neuro-symbolic processor

Abstract

This paper presents an implementation methodology of weighted ANNs whose weights have already been computed. The validation of this technique is made through the synthesis of circuits implementing the behaviour of specialised ANNs compiled from sets of logical clauses describing different logical problems. A Neuro-Symbolic Language (NSL) and its compiler5 have been designed and implemented in order to translate the neural representation of a given logical problem into the corresponding VHDL code, which in turn can set devices such as FPGA (Field Programmable Gate Array). The result of this operation leads to an electronic circuit called NSP (Neuro-Symbolic Processor) that effectively implements a massively parallel interpreter of logic programs. © Springer-Verlag Berlin Heidelberg 2003.