A 13-bit 3-MS/s asynchronous SAR ADC with a passive resistor based loop delay circuit

Abstract

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 CMOS. The ADC occupies 0.054 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.