1000-Pixels per Inch Transistor Arrays Using Multi-Level Imprint Lithography

Abstract

Sub-micrometer thin-film transistors (TFTs) are realized using multi-level imprint lithography. Amorphous indium gallium zinc oxide (α-IGZO) TFTs with channel lengths as small as 0.7μm, field-effect mobility of 10 cm2V-1s-1 and on/off ratio of circa 107 were integrated into a 1000-pixels per inch (ppi) TFT backplane array. The reduction of the number of patterning steps and the inherent self-registration of the most critical transistor layers on top of each other offer a cost-effective high-throughput fabrication route for high-resolution TFT arrays.