We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.
CITATION STYLE
Becker, B. (1992). Synthesis for testability: Binary decision diagrams. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 577 LNCS, pp. 501–512). Springer Verlag. https://doi.org/10.1007/3-540-55210-3_208
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