A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design. © 2009 Springer Berlin Heidelberg.
CITATION STYLE
Li, H. Y., Hwang, W. J., Hsu, C. C., & Hung, C. L. (2009). Efficient K-means VLSI architecture for vector quantization. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 5575 LNCS, pp. 440–449). https://doi.org/10.1007/978-3-642-02230-2_45
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